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[ a k8160b 2 ] 014003469 - e - 00 201 4 / 06 - 1 - 1. general description the ak8160b 2 is a member of akm s low power and low jitter clock generator family designed for pci express generation 2.0. t h is device has one pll with spread spectrum (ss) function and en able s to output high quality dif ferential 100mhz as pci express clock and 25mhz as reference simultaneously. 2 . features low current consumption 31 ma t yp. (full function, 25mhz output and 100mhz output) 2 5 mhz crystal input or external clock input one single - end 2 5 mhz - reference output without spread spectrum two differential 100mhz clock outputs with spread spectrum selectable s pread s pectrum on / off s pread s pectrum modulation ratio 0% (off) , - 0.5% s pread s pectrum modulation frequency 30khz to 33khz low jitter performance o f 100mhz output clock rms jitter : 2.6ps m ax . ( pcie0p - 1p/0n - 1n pin , bw=10 khz C 1.5mhz ) 2.6ps m ax . ( pcie0p - 1p/0n - 1n pin , bw=1.5mhz C 50 mhz ) cycle to cycle jitter : 125ps max. ( pcie0p - 1p/0n - 1n pin ) 23ps t yp . ( 1 ) , ( refout pin ) supply voltage 3.0v C 3.6v operating temperature range - 4 0 ? c to +85 ? c packa ge 0.4mm pitch 3mm x 3mm 20 - pin qfn (lead free) application - dslr : d igital single - lens reflex camera - network apparatus , server, datacente r - mfp : multi - function printer - game low power & low jitter clock generator for pci express ak 8160b 2
[ a k8160b 2 ] 014003469 - e - 0 0 201 4 / 06 - 2 - 3. table of contents 1. general description ................................ ................................ ................................ ................................ ........ 1 2. features ................................ ................................ ................................ ................................ .......................... 1 3. table of contents ................................ ................................ ................................ ................................ ........... 2 4. block diagram and functions ................................ ................................ ................................ ........................ 3 5. pin configurations and functions ................................ ................................ ................................ .................. 4 6. absolute maximum ratings ................................ ................................ ................................ ........................... 6 7. recommended operating conditions ................................ ................................ ................................ ............ 6 8. electrical characteristics ................................ ................................ ................................ ................................ 7 9. recommended external circuits ................................ ................................ ................................ .................. 13 10. package ................................ ................................ ................................ ................................ ....................... 14 11. important notice ................................ ................................ ................................ ................................ ......... 16
[ a k8160b 2 ] 014003469 - e - 0 0 201 4 / 06 - 3 - 4. block diagram and functions figure 1. ak8160b 2 block diagram 25[mhz] refout clock 100[mhz] pcie gen2 crystal osc xin xout vdd1 - 4 vss1 - 4 pll1 (ss) refout pcie0p pcie0n pcie1p pcie1n output divider input : 25[mhz] crystal or external clock vref ss_sel pcie1_oe refout_oe pcie0_oe
[ a k8160b 2 ] 014003469 - e - 0 0 201 4 / 06 - 4 - 5. pin configurations and functions figure 2. ak8160b 2 packag e: 20 - pin qfn (top view) pin no. pin name pin type description 1 s s_sel di ss modulation control pin this pin must be connected to h or l . ss_sel = l : modulation ratio is 0[%] (off) ss_sel = h : modulation ratio is - 0.5 [%] 2 vss3 pwr ground pi n 3 3 v dd3 pwr power supply pin 3 4 v ref ao reference voltage generation pin this pin must be connected to 1 ? f capacitor. this pin goes to hi - z when power down. 5 vdd4 pwr power supply pin 4 6 vss4 pwr ground pin 4 7 pcie1p do pci express gen2 clock o utput pin 1 (positive) this pin outputs 100mhz. 8 pcie1n do pci express gen2 clock o utput pin 1 (negative) this pin outputs 100mhz. 9 pcie0p do pci express gen2 clock o utput pin 0 (positive) this pin outputs 100mhz. 10 pcie0n do pci express gen2 clock o utput pin 0 (negative) this pin outputs 100mhz. 2 0 18 17 1 6 19 6 8 9 1 0 7 3 2 1 4 5 1 3 1 4 1 5 1 2 1 1 ss_sel vss3 vdd3 refout vss1 xin xout vss2 vdd2 v dd 4 v ref vdd1 pcie0_oe pcie1 _oe pcie 1p pcie0p pcie0n pcie 1n v ss 4 refout_oe
[ a k8160b 2 ] 014003469 - e - 0 0 201 4 / 06 - 5 - 11 pcie1_oe di pcie1p/n output control pin this pin must be connected to
[ a k8160b 2 ] 014003469 - e - 0 0 201 4 / 06 - 6 - 6. absolute maximum ratings over operating free - air temperature range unless otherwise noted (1) items symbol ratings unit supply voltage vdd - 0.3 to 4.6 v input voltage vin vss - 0.3 to vdd+0.3 v input current (any pins except supplies) i in 10 ma storage temperature tstg - 6 5 to 1 5 0 ? stress beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only. functi onal operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute - maximum - rating conditions for extended periods may affect device reliability. electrical para meters are guaranteed only over the recommended operating temperature range. this device is manufactured on a cmos process, therefore, generically susceptible to damage by excessive static voltage. failure to observe proper handling and installation pr ocedures can cause damage. akm recommends that this device is handled with appropriate precautions. 7. recommended operating conditions parameter symbol conditions min typ max unit operating temperature ta - 4 0 85 ? (1) vdd pin: vdd1 - 4 3.0 3.3 3.6 v output load capacitance cp l pin: refout 2 5 pf note: (1) power to vdd 1 C vdd4 requires to be supplied from a single source. a decoupling capacitor of 0.1f for power supply line should be connected close to each vdd pin. esd sensitive device
[ a k8160b 2 ] 014003469 - e - 0 0 201 4 / 06 - 7 - 8. electrical characteristics c urrent consumption all specifications at vdd: over 3.0v to 3.6v, ta: - 4 0 to +85 ? c, 2 5 mhz crystal, unless otherwise noted parameter symbol conditions min typ max unit current consumption 1 i dd 1 (1), (2) 31 38 ma current consumption 2 i dd 2 (1), (3) 30 37 ma current consumption 3 i dd 3 (1), (4) 0 100 ? h ( 3 ) refout output off, 100mhz output *refout_oe = l , pcie0_oe = pcie1_oe = ss_sel = h ( 4 ) full power down * refout_oe = pcie0_oe = pcie1_oe = l dc characteristics all specifications at vdd: over 3.0v to 3.6v, ta: - 4 0 to +85 ? c , 2 5 mhz crystal, unless otherwise noted parameter symbol conditions min typ max unit high level input voltage v ih refout_oe pin pcie0_oe pin pcie1_oe pin ss_sel pin 0.7 * vdd v low level input voltage v il refout_oe pin pcie0_oe pin pcie1_oe pin ss_sel pin 0.3 * vdd v input leakage current i l refout_oe pin pcie0_oe pin pcie1_oe pin ss_sel pin - 1 +1 ? re f vref pin c vref = 1 ? oh refout pin i oh = - 4ma 0.8 * vdd v low level output voltage v o l refout pin i ol = 4ma 0.2 * vdd v
[ a k8160b 2 ] 014003469 - e - 0 0 201 4 / 06 - 8 - ac characteristics (except differential output) all specifications at vdd: 3.0v to 3.6v, ta: - 4 0 to + 8 5 ? c, 2 5 mhz crystal, unless otherwise noted note: (1) specification of frequency accuracy is me asured by connecting the standard 25mhz crystal unit for part number xrcgb25m000f3m00r0 of murata manufacturing co., ltd . on page 11 . this output clock frequency accuracy does not include accuracy of crystal unit. total output clock frequency accur acy could be up to output clock frequency accuracy + crystal unit accuracy. (2) use case of external clock input (3) transition time between 0.2vdd and 0.8vdd (4) when the standard 25mhz crystal u nit is connected. (5) when the duty cycle of exte rnal clock input is 50%. (6) 1 in 10000 sampling or more (7) transition t ime to settle output into 0.1% of specified frequency after escaping power down mode. ( refout_oe pin = pcie0_oe pin = pcie1_oe pin = l ) . parameter symbol conditions min typ max unit crystal clock frequency f in_xo xin pin xout pin 2 5 .000 mhz oscillation accuracy f accuracy refout pin (1) - 30 0 +30 ppm external clock frequency f in_ext xin pin (2) 2 5 .000 mhz input clock voltage swing v swing_ext xin pin (2) 1 vdd vpp inp ut clock duty cycle t extindc xin pin (2) 50 % output frequency f osc refout pin 25.000 mhz output rising and falling t rf refout pin (3) 1.8 5.0 ns output clock duty cycle t outdc_xtal (4) refout pin 45 50 55 % t outdc_ext (5) refout pin 40 50 60 % cycle to cycle jitter ji t c2c refout pin (6) 23 48 ps output lock time t lock refout pin (7) 0.5 2 ms
[ a k8160b 2 ] 014003469 - e - 0 0 201 4 / 06 - 9 - ac characteristics (differential o utput pin : pcie0p - 1p/0n - 1n pin ) all specifications at vdd: over 3.0v to 3.6v, ta: - 4 0 to +85 ? c, 2 5 mhz crystal, unless otherwise noted note: (1) specification of frequency accuracy is measured by connecting the standard 25mhz crystal unit for part number xrcgb25m000f3m00r0 of murata manufacturing co., ltd . on page 11 . this out put clock frequency accuracy does not include accuracy of crystal unit. total output clock frequency accuracy could be up to output clock frequency accuracy + crystal unit accuracy. ( 2 ) the specifications are values applied the jitter filter func tion specified pci express standard. ( 3 ) 7 in 10000 sampling or more ( 4 ) transition t ime to settle output into 0.1% of specified frequency after escaping power down mode. (pcie0_oe pin = pcie1_oe pin = l ) . parameter symbol conditions min typ max unit average output frequency f in ss off (1) 99.97 100 .000 100.03 mhz ss on (1) 99.47 100.03 mhz output skew t slew 250 ps slew rate of output rising and falling t slew differ ential figure 6 2.5 4.0 8.0 v/ns high level output voltage v ih differential 150 mv low level out put voltage v il differential - 150 mv output cross point voltage v cross figure 4 250 550 mv output cross point voltage deviation v cross_delta figure 5 140 mv output ring back voltage margin v rb figure 9 - 100 100 mv output ring back time t stable figure 10 500 ps average clock period accuracy t period_avg - 300 2800 ppm a bsolute period t period_abs figure 8 9.847 10.203 ns maximum output voltage v max single end figure 4 1.15 v minimum output voltage v min single end figure 4 - 0.3 v output duty cycle t outdc figure 8 45 50 55 % time matching of output rising and falling t slew_delta figure 7 20 % parameter symbol conditions min typ max unit pci express gen2 rms jitter ji t rms bw= 10khz - 1.5mhz (2) 0.5 2.6 ps bw= 1.5mhz - 50mhz (2) 1.2 2.6 ps cycle to cycle jitter (p - p) ji t c2c (3) 60 125 ps output lock time t lock ss off (4) 0.5 2 ms
[ a k8160b 2 ] 014003469 - e - 0 0 201 4 / 06 - 10 - differential output measurement circuit each characteristic is measured at the point of measure point in figure 3 figure 3 . differential output measurement circuit definition of differential output ac characteristics figure 4 . definition of high / low level voltage, output cross point voltage figure 5 . definition of output cross point voltage deviation figure 6 . definition of output slew rate < 5 inch 2pf z = 10 0 ? differential traces 2pf pll core vref 3.3v measure point 1 ? f voh vcross_min= 25 0mv vcross_max=550mv voh_max= 1.15 v vol_min= - 0.3 v vol vcross pcie0/1p pcie0/1n vcross_delta_max=140mv vcross_delta pcie0/1p pcie0/1n rer differential (pcie0/1p) - (pcie0/1n) +150mv - 150mv fer
[ a k8160b 2 ] 014003469 - e - 0 0 201 4 / 06 - 11 - t slew_delta ( % ) = 100 * 2 * ( tr - tf ) / ( tr + tf ) figure 7 . definition of time m a tching of output rising and falling t outdc ( % ) = 100 * thigh / tperiod figure 8 . definition of output duty cycle figure 9 . definition of output ring back voltage margin pcie0/1p pcie0/1n vcross_m edian +75mv vcross_median - 75mv tf tr vcross_median ring back differential (pcie0/1p) - (pcie0/1n) r ing back vrb_max=100mv vrb_min= - 100mv prohibited ring back voltage range thigh 0.0v tperiod differential (pcie0/1p) - (pcie0/1n)
[ a k8160b 2 ] 014003469 - e - 0 0 201 4 / 06 - 12 - figure 10 . definition of output ring back time cry stal specification murata manufacturing co.,ltd, xrcgb25m000f3m00r0 figure 1 1 . equivalent parameter s of crystal and l oad capacitance p arameter symbol conditions min typ max unit crystal clock frequency f0 cl=6[pf] 25.000 mhz series resistance r1 56.9 150 ? tstable +150mv - 150mv tstable differential (pcie0/1p) - (pcie0/1n) crystal load capacitance cl l1 r1 c1 c0 cl
[ a k8160b 2 ] 014003469 - e - 0 0 201 4 / 06 - 13 - 9 . recommended external circuits figure 1 2 recommended external circuits pcb layout consider ation the ak8160b 2 is a hig h - accuracy and low - jitter clock generator. for proper performances specified in this datasheet, careful pcb layout should be taken. the followings are layout guidelines based on the typical connection diagram shown in figure 1 2 p ower supply line & ground pin connection ak8160b 2 has four power supply pins (vdd1 - 4 ) which deliver power to internal circuitry segments. and ak8160b 2 has four ground pins ( vss 1 - 4 ). these pin s require connecting to plane ground which will eliminate any common impedance with other cr itical switching signal return. 0.1 ? f decoupling capacitor s placed at vdd1, vdd2, vdd3 and vdd 4 should be grounded at close to the vss 1pin, the vss 2 pin, vss3 pin and the vss4 pin , respectively. crystal connection proper os cillation performance are susceptible to stray or parasitic capacitors around crystal. the wi ring traces to a crystal form x in (pin 16 ) and x out (pin 1 5 ) have equal lengths with no via and as short in length as possible. these traces should be also locat ed away from any traces with switching signal. c2 c1 c1 cext1 cext2 crystal 25 mhz c1 c1 c3 l cext1, cext2: dep e nds on crystal characteristic refer the specification of the crystal. c1 : 0.1 ? f c2 , c3 : 1 ? f 3.3v (typ) pci express device reference output 25mhz digital input l : bead 2 0 18 17 1 6 19 6 8 9 1 0 7 3 2 1 4 5 1 3 1 4 1 5 1 2 1 1 ss_sel vss3 vdd3 refout vss1 xin xout vss2 vdd2 v dd 4 v ref vdd1 pcie0_oe pcie1 _oe pcie 1p pcie0p pcie0n pcie 1n v ss 4 refout_oe
[ a k8160b 2 ] 014003469 - e - 0 0 201 4 / 06 - 14 - 1 0 . package outline dimensions 0.4mm pitch 3mm x 3mm 20 - pin qfn (unit: mm) package & lead frame material package molding compound : epoxy resin (green compound) lead frame material : cu alloy l ead frame surface treatment : au m 0 . 0 7 c a b 0 . 0 5 c b 3 . 0 0 0 . 0 5 3 . 0 0 0 . 0 5 0 . 0 5 m a x 0 . 7 5 0 . 0 5 1 . 9 0 0 . 1 0 1 . 9 0 0 . 1 0 c 0 . 2 5 0 . 3 0 . 0 5 0 . 2 0 0 . 0 5 1 5 6 1 0 1 1 1 5 1 6 2 0 a 0 . 4 0 b s c
[ a k8160b 2 ] 014003469 - e - 0 0 201 4 / 06 - 15 - marking a: #1 pin index : circle b: part number : 60b 2 c: date code : 4 digits revision history date revision reason page/line contents 1 4 / 06 / 2 7 00 initial release. 2 0 18 17 1 6 19 6 8 9 1 0 7 3 2 1 4 5 1 3 1 4 1 5 1 2 1 1 xxxx 60b 2
[ a k8160b 2 ] 014003469 - e - 0 0 201 4 / 06 - 16 - 1 1 . impo rtant notice important notice 0. asahi kasei microdevices corporation (akm) reserves the right to make changes to the information contained in this document without notice. when you consider any use or application of akm product stipulated in t his document ( product ) , please make inquiries the sales office of akm or authorized distributor s as to current status of the products. 1. all information included in this document are provided only to illustrate the operation and application examples of akm products . akm neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of akm or any third part y with respect to the information in this document. you are fully responsible for use of such information contained in this document in your product design or applications . akm assumes no liability for any losses incurred by you or third parties arising fr om the use of such information in your product design or applications. 2. the product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact , including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for auto mobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance - related fields. do not use product for the above use unless specifically agreed by akm in writing . 3. though akm works continually to improve the products quality and reliability, you are responsible for complying with safety standards and for providing adequate designs an d safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. do not use or otherwise make available the product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, o r biological weapons or missile technology products (mass destruction weapons). when exporting the p roducts or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and f ollow the procedures required by such laws and regulations. the p roducts and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. please contact akm sales representative for details as to environmental matters such as the rohs compatibility of the product. please use the product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. akm assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. resale of the product with provisions different fr om the statement and/or technical features set forth in this document shall immediately void any warranty granted by akm for the product and shall not create or extend in any manner whatsoever , any liability of akm. 7. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of akm .

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